1. Field of the Invention
The present invention is generally in the field of integrated circuits. More specifically, the invention is in the field of ESD protection for integrated circuits.
2. Related Art
MOSFET snap-back devices, such as snap-back NFETs, have been used as electrostatic discharge (ESD) clamp devices as well as to protect I/O driver transistors from ESD damage. Snap-back in a MOSFET involves the triggering of a parasitic lateral bipolar transistor into a conducting mode, which is sustained by impact ionization current generated from the collector current. By way of background, the source, body, and drain of the MOSFET form, respectively, the emitter, base, and collector of a parasitic lateral bipolar transistor. Unfortunately, because of the negative resistance characteristic of snap-back, conduction can be non-uniform such that only a portion of the transistor conducts at the point where a leakage failure occurs.
A number of conventional methods have been incorporated into the MOSFET to improve snap-back conduction uniformity. In one conventional method, a drain resistor is used to extend the voltage of a conducting region's failure point. The higher failure voltage afforded by the inclusion of the drain resistor allows the drain voltage to reach the conduction trigger voltage of other, “off” regions before failure of the region that is already in the conducting or “on” state. Unfortunately, the resistor adds considerable area and drain capacitance to the structure layout. Also, since the incorporation of salicide into processes, a salicide block mask is required to make the diffusion resistor, which requires an additional processing step.
Thus, there is a need in the art for a MOSFET device having improved snap-back conduction uniformity for more effective ESD protection.